Connections for memory electrode lines

ABSTRACT

Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.

CROSS REFERENCE

The present Application for Patent is a continuation of U.S. patentapplication Ser. No. 16/871,957 by Castro, entitled “Connection forMemory Electrode Lines,” filed May 11, 2020, which is a continuation ofU.S. patent application Ser. No. 16/057,603 by Castro, entitled“Connection for Memory Electrode Lines,” filed August 7, 2018, which isa continuation of U.S. patent application Ser. No. 14/637,158 by Castro,entitled “Connection for Memory Electrode Lines,” filed Mar. 3, 2015;each of which is assigned to the assignee hereof, and each of which isexpressly incorporated by reference herein.

TECHNICAL FIELD

Embodiments of the present invention generally relate to integratedcircuits and more specifically to architectures for cross-point memorydevices.

BACKGROUND

There are many different types of memory, including random-access memory(RAM), read only memory (ROM), dynamic random access memory (DRAM),synchronous dynamic random access memory (SDRAM), resistive memory, andflash memory, among others. Types of resistive memory include phasechange memory, programmable conductor memory, and resistive randomaccess memory (RRAM), among others. Memory devices are utilized asnon-volatile memory for a wide range of electronic applications in needof high memory densities, high reliability, and data retention withoutpower. Non-volatile memory may be used in, for example, personalcomputers, portable memory sticks, solid state drives (SSDs), digitalcameras, cellular telephones, portable music players such as MP3players, movie players, and other electronic devices. Various resistivememory devices can include arrays of cells organized in a cross pointarchitecture. In such architectures, the memory cells can include a cellstack comprising a storage element, e.g., a phase change element, inseries with a select device, e.g., a switching element such as an ovonicthreshold switch (OTS) or diode, between a pair of conductive lines,e.g., between an access line and a data/sense line. The memory cells arelocated at the intersections of word lines and bit lines and can be“selected” via application of appropriate voltages thereto.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is an isometric view of a portion of a deck of a memory array,according embodiments.

FIG. 1B is an isometric view of a portion of a dual-deck memory array,according to embodiments.

FIG. 2A is an illustration of one memory architecture in which an activememory array is partitioned into multiple sub-arrays with drivercircuitry interspersed within the array region, according to onearrangement.

FIG. 2B is an illustration of socket interconnect regions for connectingword lines and bit lines of FIG. 2A to their drivers.

FIG. 3A is an illustration of one array architecture having an activememory array partitioned into multiple sub-arrays with socketinterconnect regions interspersed within the active memory array,according to another arrangement.

FIG. 3B is a more detailed illustration of one of the sub-arrays of thearray of FIG. 3A with socket interconnect regions interspersed withinthe active memory array.

FIG. 3C is a close-up view of a gap region including a socketinterconnect region of the array architecture of FIG. 3A.

FIG. 4A is an illustration of one array architecture having an activememory array partitioned into multiple sub-arrays with socketinterconnect regions interspersed within the active memory array,according to another arrangement.

FIG. 4B is a more detailed illustration of one of the sub-arrays of thearray of FIG. 4A with socket interconnect regions interspersed withinthe active memory array.

FIG. 4C is a close-up view of a gap region including a socketinterconnect region of the array architecture of FIG. 4A.

FIG. 5A is a schematic illustration of one array architecture having anactive memory array partitioned into multiple sub-arrays with socketinterconnect regions interspersed within the active memory array,according to an embodiment.

FIG. 5B is a more detailed view of one of the sub-arrays of the array ofFIG. 5A with socket interconnect regions interspersed within the activememory array, according to an embodiment.

FIG. 5C is a close-up view of a gap region including a socketinterconnect region of the array architecture of FIG. 5A, according toan embodiment.

FIG. 5D is a close-up view of a plurality of sub-arrays of FIG. 5Aillustrating adjacent electrode lines that are shifted with respect toeach other, according to an embodiment.

FIG. 6A is a schematic cross-sectional view of a memory deviceillustrating vertical connections and metallization structures for thememory array architecture illustrated in FIGS. 3A-3C, according to onearrangement.

FIG. 6B is a cross-sectional view of a memory device illustratingvertical connections and metallization structures for the memory arrayarchitecture illustrated in FIGS. 4A-4C, according to anotherarrangement.

FIG. 6C is a cross-sectional view of a memory device illustratingvertical connections and metallization structures for the memory arrayarchitecture illustrated in FIGS. 5A-5D, according to an embodiment.

Reference is made in the following detailed description to theaccompanying drawings, which form a part hereof, wherein like numeralsmay designate like parts throughout to indicate corresponding oranalogous elements. It will be appreciated that for simplicity and/orclarity of illustration, elements illustrated in the figures have notnecessarily been drawn to scale. For example, the dimensions of some ofthe elements may be exaggerated relative to other elements for clarity.Further, it is to be understood that other embodiments may be utilized.Furthermore, structural and/or logical changes may be made withoutdeparting from the scope of claimed subject matter. It should also benoted that directions and/or references, for example, up, down, top,bottom, and so on, may be used to facilitate discussion of drawings andare not intended to restrict application of claimed subject matter.Therefore, the following detailed description is not to be taken tolimit the scope of claimed subject matter and/or equivalents.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are setforth to provide a thorough understanding of claimed subject matter.However, it will be understood by those skilled in the art that claimedsubject matter may be practiced without these specific details. In otherinstances, methods, apparatuses and/or systems that would be known byone of ordinary skill have not been described in detail so as not toobscure claimed subject matter.

Integrated circuits, such as integrated circuit memory devices, includemultiple layers of material typically built on a substrate. The materiallayers include metal and other highly conductive layers that arepatterned into conductive lines and other circuit elements. Elongateconductive lines in an integrated circuit include interconnects; linesthat also function as electrodes for semiconductor devices (e.g.,switches and/or memory storage elements) can be referred to as electrodelines. Conductive lines formed from a layer or layers at the samevertical level can be referred to collectively as a metal level, thoughthe material can be formed from non-metal conductors such as dopedsemiconductor layers (e.g., polysilicon) or metallic alloys such asmetal nitrides, metal carbides and metal silicides. Contacts formedbetween metal levels can be referred to as vertical connectors orcontact vias. Such vertical connectors can be formed separately from thelines they connect, or can be simultaneously formed with overlyingconductive lines in a dual damascene process.

Furthermore, digit lines can be referred to as column electrodes, andreferences to digit line drivers and driver regions herein are moregenerally applicable to column drivers and driver regions. An example ofa digit line is a “bit line.” Similarly, word lines can be referred toas row electrodes, and references herein to word line drivers and driverregions are more generally applicable to row drivers and driver regions.The skilled artisan will appreciate that row and column electrodes neednot be perpendicular; rather, an array can be configured in a manner inwhich the row and column electrodes cross one another atnon-perpendicular angles.

In embodiments described herein, row and column driver regions (or wordline and digit line driver regions) are described as including rowdriver circuits and column driver circuits. In addition to drivercircuitry, the circuit level described below can include distributed orcontiguous additional circuitry for operation of the memory array withinthe shared footprint with a memory array, such as global drivers,repeaters, write circuits, sense amplifiers, word decoders, digitdecoders, etc. Collectively these circuits can be referred to as logiccircuitry for the memory array. For example, digit line drivers, sensecircuitry and digit decoders can be formed within column driver regions;word line drivers, word decoders, write circuits, global drivers andrepeaters can be formed within column drivers. The skilled artisan willappreciate that different types of logic circuits can be distributeddifferently among the row and column driver regions described herein,and that in some embodiments the additional circuitry can be within thefootprint of the memory array but outside the driver regions. Some typesof logic circuitry can remain outside the footprint of the memory array.

A memory device may include an array of memory cells. A memory arraygenerally includes two or more conductive, or semi-conductive, sets oforthogonal lines referred to as access lines, such as row electrodes inthe form of word lines, and data/sense lines, such as column electrodesin the form of digit lines, that are used to program, erase, and readmemory cells. Word lines and digit lines can also serve as electrodesfor the memory cells. Although different types of memory cells may beprogrammed, erased, and read in different manners, word lines and digitlines are typically coupled to respective word line and digit linedriver circuitry. As used herein, the term “substrate” may includesilicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology,doped and undoped semiconductors, epitaxial layers of silicon supportedby a base semiconductor foundation, complementary metal oxidesemiconductors (CMOS), e.g., a CMOS front end with a metal backend,and/or other semiconductor structures and technologies. Variouscircuitry, such as decode circuitry, for example, associated withoperating memory array may be formed in and/or on the substrate.Furthermore, when reference is made to a “substrate” in the followingdescription, previous process steps may have been utilized to formregions or junctions in the base semiconductor structure or foundation.

FIG. 1A is an isometric view of a memory array 100 that may be includedin an integrated circuit device. The memory array 100 is formed over asubstrate (not shown, e.g., a silicon substrate), in which variouscircuitry, such as drivers and decode circuitry, associated withoperating the memory array may be formed in and/or on the substrate. Inaddition, as described below with respect to FIGS. 6A-6C, the memoryarray 100 and the substrate may be electrically connected via one ormore metallization layers which connect the various circuitry to thememory array 100.

In the illustrated embodiment, the memory array 100 is a cross pointmemory array having a plurality of variable resistance memory cells 30at intersections between a plurality of column lines 20 extending in ay-direction and a plurality of row lines 22 formed extending in anx-direction. Each memory cell 30 is a variable resistance memory celland can change between first and second resistance states in response toelectrical signals. In the illustrated embodiment, each memory cell 30has a cell stack comprising a storage element 34 and a selector element38 that are configured to be electrically accessed through one of thecolumn lines 20, which can be a digit line, and one of the row lines 22,which can be a word line. Each memory cell 30 further includes a firstelectrode 32 connecting the column line 20 and the storage element 34, amiddle electrode 36 connecting the storage element 34 and the selectorelement 38, and a second electrode 40 connecting the selector element 38and the row line 22. Adjacent memory cells 30 can be separated byisolation dielectrics 48. While only four memory cells 30 are depictedfor clarity, it will be understood that the column lines 20 and rowlines 22 can extend further to include an arbitrary number of memorycells 30.

In some embodiments, the variable resistance memory cell 30 is a phasechange memory cell in which one or both of the selector element 38 andthe storage element 34 can comprise chalcogenide materials. When boththe selector element 38 and the storage element 34 comprise chalcogenidematerials, the storage element 34 can comprise a chalcogenide materialthat can undergo a phase change that is stable and nonvolatile at roomtemperature. On the other hand, the selector element 38 can comprise achalcogenide material that does not undergo a similar stable andnonvolatile phase change. When the storage element 34 includes achalcogenide material, the variable resistance memory cell 30 may bereferred to as a phase change memory cell.

Examples of chalcogenide materials included in the storage element 34include chalcogenide compositions such as an alloy including at leasttwo of the elements within the indium(In)-antimony(Sb)-tellurium(Te)(IST) alloy system, for example, In2Sb2Te5, IniSb2Te4, IniSb4Te7, etc.,or an alloy including at least two of the elements within thegermanium(Ge)-antimony(Sb)-tellurium(Te) (GS T) alloy system, forexample, Ge8Sb5Te8, Ge2Sb2Te5, GeiSb2Te4, GeiSb4Te7, Ge4Sb4Te7, etc.Other chalcogenide alloy systems that can be included in the storageelement 34 include Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te,In—Ge—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb,Ga—Se—Te, Sn—Sb—Te, In—Sb—Ge, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au,Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—Sb—Te—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se,Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, Ge—Te—Sn—Ni, Ge—Te—Sn—Pd, andGe—Te—Sn—Pt, for example. The hyphenated chemical composition notation,as used herein, indicates the elements included in a particular mixtureor compound, and is not intended to represent a particular stoichiometryinvolving the indicated elements.

Examples of chalcogenide-based selector element 38 include atwo-terminal selector comprising a chalcogenide material, which issometimes referred to as an Ovonic Threshold Switch (OTS). An OTS mayinclude a chalcogenide composition including any one of the chalcogenidealloy systems described above for the storage element 34. In addition,the selector element 38 may further comprise an element such as tosuppress crystallization. Examples of OTS materials include Te—As—Ge—Si,Ge—Te—Pb, Ge—Se—Te, Al—As—Te, Se—As—Ge—Si, Se—As—Ge—C, Se—Te—Ge—Si,Ge—Sb—Te—Se, Ge—Bi—Te—Se, Ge—As—Sb—Se, Ge—As—Bi—Te, and Ge—As—Bi—Se,among others.

Examples of non-chalcogenide-based selector elements include a twoterminal device (e.g., a switch), such as a diode, an ovonic thresholdswitch (OTS), a tunnel junction, or a mixed ionic electronic conductionswitch (MIEC), among other two terminal devices. Alternatively, examplesof the selector element include a three terminal device (e.g., aswitch), such as a field effect transistor (FET) or a bipolar junctiontransistor (BJT), among other switching elements.

One advantage of cross point memory arrays such as the memory array 100described above with respect to FIG. 1A is that arrays of memory cellscan be physically stacked on top of one another, such that the physicaldensity of memory cells can be increased, e.g., doubled, tripled,quadrupled, etc., without incurring additional lateral array footprint.In the following, a stack of memory cells electrically addressable bytwo sets of conductive lines, e.g., digit lines and word lines, isreferred to herein as a “deck.”

FIG. 1B is an isometric view of a dual-deck memory array 200, which maybe a dual-deck variable resistance memory array 200, which includes alower deck 94 and an upper deck 98. The lower deck 94 includes firstconductive lines 22 extending in an x-direction, in a similar manner tothe lower conductive lines 22 of FIG. 1A, and second conductive lines 20extending in a y-direction in a similar manner to the upper conductivelines 20 of FIG. 1A. Similar to FIG. 1A, the lower deck 94 furtherincludes a plurality of lower variable resistance memory cells 92 formedon the first conductive lines 22. Adjacent variable resistance memorycells 92 can be separated in the y-direction and in the x-direction byisolation dielectrics 48 and 50, respectively. For illustrativepurposes, the lower variable resistance memory cells 92 will bedescribed herein as phase change memory cells, but other variableresistance memory cells can be used in other arrangements, as describedabove. The lower phase change memory cells 92 include a first lowerelectrode line 40 extending in the x-direction, a first lowerchalcogenide element 38 disposed on the first lower electrode line 40, afirst middle electrode 36 disposed on the first lower chalcogenideelement 38 (e.g., a selector node), a first upper chalcogenide element34 (e.g., a storage node) on the first middle electrode 36, and a firstupper electrode 32 disposed on the first upper chalcogenide element 34.

In the illustrated dual-deck memory array 200, the upper deck 98 sharescommon conductive lines with the lower deck 94 as access lines. Theupper deck 98 includes the second conductive lines 20 extending in they-direction that are shared as access lines with the lower deck 94, andfurther includes third conductive lines 24 extending in the x-direction.Upper variable resistance memory cells 96 are disposed on the secondconductive lines 20. Each upper variable resistance memory cell 96include a second lower electrode line 80 extending in the y-direction, asecond lower chalcogenide element 78 disposed on the second lowerelectrode line 80, a second middle electrode 76 disposed on the secondlower chalcogenide element 78 (e.g., a selector node), a second upperchalcogenide element 74 (e.g., a storage node) on the second middleelectrode 76, and a second upper electrode 72 disposed on the secondupper chalcogenide element 74. Adjacent upper variable resistance memorycells 96 can be separated in the y-direction and in the x-direction byisolation dielectrics 54 and 50, respectively.

In addition to being configurable as a plurality of decks of memoryarrays for multiplying the physical bit density by the number of decks,because one or more decks of memory cell stacks 200 described above canbe formed above the substrate, various support circuitry, such as decodecircuitry and/or driver circuitry associated with operating the memoryarray, may be disposed under the memory array. As a result, the amountof independent lateral footprint occupied by the support circuitry maybe dramatically reduced or even eliminated, compared to exclusivelyperipherally located support circuitry, thereby increasing the overallarray layout efficiency, according to various embodiments disclosedherein. Furthermore, according to various embodiments described herein,the support circuitry may be arranged in an interlaced or interweavedpattern under the memory array such that socket connections forelectrically connecting the array electrode lines, e.g., word lines anddigit lines, to the underlying support circuitry can be formed usingreduced criticality of lithography processes, while improving electricalaccess performance, e.g., reducing RC delay of the electrode lines, andimproving efficiency of connections to electrode lines of differentdecks.

FIG. 2A illustrates a memory architecture in which word line drivers 212and digit line drivers 214 are distributed and disposed substantiallywithin the foot print of the active array, e.g., disposed under andoverlapping the memory cells of the memory array, according onearrangement. It will be understood that each shaded area comprises aregion that can include multiple driver circuits, e.g., multiple unitsof CMOS circuits. FIG. 2A depicts one of repeating memory array units,referred to herein as a tile 202 of memory array. As shown, the tile 202has at least one word line 230 a traversing substantially an entirewidth of the tile 202 in the x-direction before terminating at or withinword line socket interconnect regions 224 (described below with respectto FIG. 2B) disposed at opposing edges of the tile 202 extending they-direction. Similarly, the tile 202 has at least one digit line 220 atraversing substantially an entire length of the tile 202 in they-direction before terminating at or within digit line socketinterconnect regions 222 (described below with respect to FIG. 2B)disposed at opposing edges of the tile 202 extending in the x-direction.In some embodiments, the tile 202 can have CMOS decoders within itsfootprint that are used to select each distinct word line (230 a, 230 b)and each distinct digit line (220 a, 220 b) that are disposed within thetile.

The tile 202 of memory array in FIG. 2A is divided into four sub-units(quadrants), referred to herein as patches 204, 206, 208 and 210 of thetile 202 of memory array. In the illustrated embodiment, each word line(230 a, 230 b) traverses two patches (204 and 206 or 208 and 210) in thex-direction before terminating and each digit line (220 a, 220 b)traverse two patches (204 and 210 or 206 and 210) in the y-directionbefore terminating. Two patches traversed by a word line or a digit linecan be of adjacent tiles 202.

In the tile 202 of FIG. 2A, each patch in a plan view is identical to aneighboring patch such that adjacent patches have corresponding wordline drivers 212 and digit line drivers 214 that repeat in x- ory-directions. The word line drivers 212 are in the upper left and lowerright corners of each patch, and extend generally along the edgesextending in the y-direction to connect with word lines 230 a and 230 bextending in the x-direction. The digit line drivers 214 are in theupper right and lower left corners of each patch, and extend generallyalong the edges extending in the x-direction to connect with digit lines220 extending in the y-direction. In an example PCM array, the fourpatches 204, 206, 208 and 210 can occupy the same footprint as betweenabout 100 thousand and 16 million memory cells, depending on the numberof decks of memory each tile includes. The digit line drivers 214 andword line drivers 212 are typically formed within the semiconductorsubstrate below the digit lines 220 and word lines 230. The socketinterconnect regions, described below, are the regions in which thedigit lines 220 and word lines 230 are connected to interconnectcircuitry, and thus indirectly to the drivers.

Other non-repeating patch arrangements are possible, where adjacentpatches do not repeat the patterns of the drivers but can be symmetric“mirror images.” Examples of such arrangements are described withrespect to FIGS. 3A-3C, 4A-4C and 5A-5D. For example, patches 204 and206 can be minor-symmetric to each other about the mutual boundaryextending in the y-direction. In such configurations, the lower ones ofthe two word line drivers 212 of the patches 204 and 206 would beimmediately adjacent each other while the upper ones of the two wordline drivers 212 would be disposed at the two opposing sides of the tile202 that extend in the x-direction. In the illustrated embodiment, eachof the patches 204, 206, 208, 210 has a width X1 in the x-direction anda length Y1 in the y-direction.

Still referring to FIG. 2A, word line drivers 212 may be coupled to acentral location of each word line 230 a/230 b, which may crossboundaries between adjacent patches. The word lines 230 a, 230 b canhave generally the same length, e.g., 2X1, as illustrated. As indicatedby a dot along each word line 230 a/230 b, a socket, which represents aconnection point between the word line 230 a/230 b to its driver 212(typically indirectly through interconnect lines) is generallypositioned centrally, e.g., closer to a mid-point along the word line230 a/230 b than to either end point (indicated by an arrow head) of theword line 230 a/230 b. In some implementations, the socket is positioneda distance of at least 40% of the length of the word line 230 a/230 bfrom either end of the word line 230 a/230 b, i.e., along the middle 20%of the length of the word line. The total number of digits, e.g., bits,coupled to a physical word line may be the same as a conventionalend-connected word line, and can be the same for each word line in thearray, although the distance to the terminal point of the word line fromthe driver interconnect may vary.

The digit line drivers 214 are coupled to central location of each digitline 220 a/220 b, in a similar manner as described above with respect tothe word lines 230 a/230 b. Similar to word lines 230 a/230 b, the digitlines 220 a, 220 b cross boundaries between adjacent patches and cangenerally have the substantially the same length, e.g., 1Y1. Furthersimilar to the word lines, each digit line 220 a/220 b can be connectedto its driver 214 (typically indirectly through interconnect lines) by asocket, represented by a dot, that is positioned centrally along thedigit line, e.g., closer to a mid-point of the digit line than to eitherend points, or e.g., positioned a distance of at least 40% of the lengthof the digit line from either end of the digit lines, i.e., along themiddle 20% of the length of the word line. The total number of digits,e.g., bits, coupled to a physical digit line may be the same as aconventional end-connected digit line, and can be the same for eachdigit line in the array, although the distance to the terminal point ofthe word line from the driver interconnect may vary.

It will be appreciated that the driver circuits can be reversed, forexample the word line drivers can be in the lower left and upper rightcorners of the patches, as long as all patches have the same layout.

FIG. 2B illustrates socket interconnect regions 224 for the word linesand socket interconnect regions 222 for the digit lines of the arrayarchitecture of FIG. 2A. It is noted that the socket interconnectregions are disposed at the boundaries of each of the patches 204, 206,208 and 210 and can partially overlap edge regions of adjacentneighboring patches. That is, a common word line socket interconnectregion 224 extends in the y-direction and is disposed between twopatches that are adjacent each other in the x-direction, e.g., patches204 and 206, or patches 208 and 210. Similarly, a common digit linesocket interconnect region 222 extends in the x-direction and isdisposed between two patches that are adjacent each other in they-direction, e.g., patches 204 and 210, or patches 206 and 208.

From a frame of reference of the tile 202, FIGS. 2A and 2B illustratetwo types of word lines 230 a and 230 b and two types of digit lines 220a and 220 b. The word lines 230 a are centrally connected at or withinone of the inner word line socket interconnect regions 224, andterminate at or within one of the outer word line socket interconnectregions 224 formed along the edge regions of the tile 202 that extend inthe y-direction. The word lines 230 b are centrally connected at orwithin one of the outer word line socket interconnect regions 224 formedalong the edge regions of the tile 202 that extend in the y-direction,and terminate at or within one of the inner word line socketinterconnect regions 224. As a result, the word lines 230 a/230 b areeither connected or terminate at or within one of the word line socketinterconnect regions 224, while no word line 230 a/230 b passes throughany of the word line socket interconnect regions 224 without connectionor termination.

Similarly, the digit lines 220 a are centrally connected at or withinone of the inner digit line socket interconnect regions 222, andterminate at or within one of the outer digit line socket interconnectregions 222 formed along the edge regions of the tile 202. The digitlines 220 b are centrally connected at or within one of the outer digitline socket interconnect regions 222 formed along the edge regions ofthe tile 202 that extend in the x-direction, and terminate at or withinone of the inner digit line socket interconnect regions 222. As aresult, the digit lines 220 a/220 b are either connected or terminate ator within one of the digit line socket interconnect regions 222, whileno digit line 220 a/220 b passes through any of the digit line socketinterconnect regions 222 without connection or termination.

It has been found that, by increasing the degree of subdivision of amemory tile into patches and having different degrees of interlacing oroffsetting of electrode lines, certain advantages can be achieved, e.g.,looser lithographic requirements for interconnect structures thatconnect the electrode lines to metallization levels below the memoryarray. In the following, with respect to embodiments of FIGS. 3A-3C,4A-4C and 5A-5D, various arrangements of tiles of memory arrays that aresubdivided into patches at varying degrees are disclosed. Socketinterconnect regions serve as connecting regions for connecting aplurality of electrode lines formed at a first vertical level tointerconnect structures formed at a vertical level different from, e.g.,lower than, the vertical level at which the electrode lines are formed.In some arrangements, the electrode lines include a plurality ofcontacted lines that are vertically connected to the interconnectstructures at a socket interconnect region (FIGS. 3A-3C, 4A-4C and5A-5D). In some other arrangements, the electrode lines additionallyinclude a plurality of terminating lines terminating at the socketinterconnect region (FIGS. 4A-4C and 5A-5D). In some embodiments, theelectrode lines additionally includes a plurality of pass-through linesthat pass through the socket interconnect region without beingvertically connected and without being terminated at the socketinterconnect region (FIGS. 5A-5D).

In some embodiments, as described in more detail below with respect toFIG. 5C and 5D, each of the conductive lines is connected at arespective socket interconnect region to the interconnect structures,wherein at least one of the conductive lines is connected at a firstsocket interconnect region and at least another one of the electrodelines is connected at a second socket interconnect region that isshifted in the first direction relative to the first socket interconnectregion by less than about one quarter of a length of the electrodelines, for instance between about 5% and about 20% of a length of theelectrode lines.

In various arrangements described more in detail below with respect toFIGS. 3C, 4C and 5C, a plurality of electrode lines, e.g., parallellines, extend in a first direction (e.g., x-direction) and have regularline widths and widths of spaces between the lines such that the lineshave a first pitch in the second direction (e.g., y-direction) crossingthe first direction. Each electrode line is connected to interconnectstructures disposed at a vertical level different from the verticallevel of the electrode lines at a respective vertical connectionposition, e.g., metallization levels below the level of the electrodelines.

As will be explained in more detail in reference to FIGS. 5D and FIGS.6A-6C, in various arrangements, the vertical connection positions alongthe first direction of some electrode lines may be shifted relative toone another in the first direction, while the vertical connectionpositions along the first direction of some other electrode lines may bedisposed at a similar or the same vertical connection positions and notbe shifted relative to one another in the first lateral direction. Inaddition, the similar or the same vertical connection positions mayperiodically repeat in the second direction at a periodicity that isgreater than the first pitch, e.g., greater than at least three timesthe first pitch, for instance four times the first pitch or eight timesthe first pitch. For example, in some embodiments, each electrode linemay have a vertical connection position that is shifted in thex-direction with respect to an immediately adjacent electrode line by afraction, e.g., ¼, ⅛, 1/16, etc., of the electrode line length. Inaddition, successive adjacent lines may continue to shift in a regularpattern in the second direction, such that two electrode lines separatedby a number of intervening lines may have the same vertical connectionposition in the x-direction. For example, where immediately adjacentelectrode lines are successively shifted in the x-direction by ¼, ⅛ and1/16 of the electrode line length, the vertical connection positions maybe repeated in the y-direction every 4, 8 and 16 lines, respectively. Inthese arrangements, the electrode lines have a pitch of 2 F, thecorresponding periodicity of the vertical connection positions in they-direction would be 8 F, 16 F and 32 F, respectively. In otherembodiments, immediately adjacent lines are shifted by differentmultiples of a fraction of the electrode line length. In some otherembodiments, instead of individual lines being shifted relative to oneanother, groups of lines, e.g., pairs of lines, may be shifted relativeto one another, e.g., in the case where the lines are patterned by apitch multiplication technique. For example, each pair of electrodelines may have a vertical connection position that is shifted in thex-direction with respect to an immediately adjacent pair of electrodelines by a fraction, e.g., ¼, ⅛, 1/16, etc., of the electrode linelength. In these embodiments, immediately adjacent pairs of electrodelines are shifted in the x-direction by ¼, ⅛ and 1/16 of the electrodeline length, such that the vertical connection positions may be repeatedin the y-direction every 16, 32 and 64 lines, respectively.

As described herein, in some embodiments, an electrode line whichextends in a given direction can include jogs or kinks within the line.The direction of such line, however, generally begins and ends in thesame direction and the jogs are only short deviations from the generaldirection of extension. Such jogs are illustrated, for example, in USPatent Publication No. 2014-0239512, published on Aug. 28, 2014.

Varying degrees of subdivision can be utilized to optimize the socketinterconnection to an underlying driver region. In each of thearrangements, while not shown for clarity, it will be understood that aword line driver is located substantially within the foot print ofactive array, e.g., near the edges of a patch, in a similar manner asdescribed above with respect to FIGS. 2A and 2B. Similarly, it will beunderstood that a digit line driver is located substantially within thefoot print of active array, e.g., near the edges of a patch, in asimilar manner as described above with respect to FIGS. 2A and 2B. Inaddition, while not illustrated, it will be understood that each socketinterconnect region at least partially overlaps a corresponding driverregion, in a similar manner as illustrated above with respect to FIGS.2A and 2B, but maybe be shifted from the horizontal location of thecorresponding socket region by connection through multiple levels ofinterconnect metallization. In addition, it will be understood that eachshaded area comprises a region that can include multiple drivercircuits.

In the following with respect to FIGS. 3A, 4A and 5A, while a singletile is illustrated, in practice any number of tiles can be joinedtogether to form a larger memory array. In each of the arrangements ofmemory tiles described below with respect to FIGS. 3A-3C, 4A-4C and5A-5D, each patch of a memory tile comprises a “mirror copy” of anadjacent patch, in contrast to the memory patches described with respectto FIG. 2A. In each of the arrangements, word line socket interconnectregions are disposed in the lower left and upper right corners of eachpatch and extend generally in the y-direction, and digit line socketinterconnect regions are disposed in the upper left and lower rightcorners of each patch and extend generally in the x-direction. In eachof the memory tiles described below with respect to FIGS. 3A-3C, 4A-4Cand 5A-5D, a digit line spans a length of 2Y1 that is equivalent to alength in the y-direction of one tile, and a word line spans a length of2X1 that is equivalent to a width in the x-direction of one tile. Inother words, the dimensions of the tile are defined as equal to thelengths of the words lines and digit lines. However, in each of thememory tiles described below with respect to FIGS. 3A-3C, 4A-4C and5A-5D, the number of patches spanned by a digit line in the x-directionand the number of patches spanned by a word line in the y-direction aredifferent, as described below. In each of FIGS. 3A-3B, 4A-4B and 5A-5B,in a similar manner as described in FIG. 2A, vertical connectionlocations within a socket region, of word lines and digit lines areindicated by dots, and termination locations of word lines and digitlines are indicated by arrow heads. In each of FIGS. 3A-3B, 4A-4B and5A-5B, in a similar manner as described above with respect to FIG. 2A,while a single double-sided arrow may be used to designate a word lineor a digit line, it will be understood that there is a plurality ofsimilar word lines or digit lines within a given socket interconnectregion. As described herein, a main array region refers to a region ofmemory array where electrode lines of different types, e.g., the digitlines and word lines, cross each other to form memory cells. A gapregion, also referred to herein as a boundary region, refers to a regionbetween main array regions in which electrode lines of different typesdo not cross each other. A gap region can include an electrode socketinterconnect region and a terminating electrode line region and/or apass-through electrode line region. The electrode socket interconnectregion and the terminating electrode line region and/or the pass-throughelectrode line region may be laterally adjacent to each other. Anelectrode socket interconnect region includes a plurality of verticallyconnected lines. A terminating electrode line region does not includevertically connected lines and includes electrode lines terminatingtherein. A pass-through electrode line region does not includevertically connected lines and includes electrode lines that passtherethrough.

FIG. 3A illustrates a tile 304 of memory array divided into four (2×2)patches 308, and FIG. 3B illustrates one of the patches 308 of the tile304, according to some arrangements. From a frame of reference of theillustrated tile 304, FIGS. 3A and 3B illustrate two types of wordlines. Word lines 330 a are vertically connected at their respectivecentral locations at or within one of inner word line socketinterconnect regions 312 located in the upper and lower middle regionsof the tile 304. Word lines 330 b are vertically connected at theirrespective central locations at or within one of outer word line socketinterconnect regions 312 located in the left and right middle edgeregions of the tile 304, which are shifted in the x-direction by about ½of a length of the word lines, e.g., by X1, and further shifted in they-direction by about ½ of a length of the digit lines, e.g., by Y1. Inthe tile 304, each digit line 320 a/b spans between one and threepatches 308 in the y-direction, for instance about two patches 308,while each word line 330 a/b spans between one and three patches 308 inthe x-direction, for instance about two patches 308. Unlike the wordlines of FIG. 2A, the word lines 330 a and 330 b do not terminate at orwithin another one of one of the word line socket interconnect regions.Instead, the word lines 330 a and 330 b terminate within a terminatingword line region 316 (FIG. 3B) between adjacent patches and outside theword line socket interconnect regions 312. Similarly, FIGS. 3A and 3Billustrate two types of digit lines. Digit lines 320 a are verticallyconnected at their respective central locations at or within the innerdigit line socket interconnect region 314 located in the central regionof the tile 304. Digit lines 320 b are vertically connected at theirrespective central locations at or within the outer digit line socketinterconnect regions 314 at upper right, upper left, lower right andlower left regions of the tile 304. Unlike the digit lines of FIG. 2A,the digit lines 330 a and 330 b do not terminate at or within anotherone of one of the digit line socket interconnect regions. Instead, thedigit lines 330 a and 330 b terminate within a terminating digit lineregion 318 (FIG. 3B) that is outside the digit line socket interconnectregions and outside the main array regions.

In some arrangements, within a given patch 308, word lines 330 acomprise about half the word lines, and word lines 330 b comprise aremainder of the word lines. Similarly, in some embodiments, digit lines320 a comprise about half the digit lines, and digit lines 320 bcomprise a remainder of the digit lines.

FIG. 3C illustrates a detailed view of a boundary region 340 betweenmain array regions of adjacent patches 308 in the x-direction, for thearchitecture described with respect to FIGS. 3A-3B. The boundary region340 includes a word line socket interconnect region 312 and aterminating word line region 316. The boundary region 340 is formedbetween main array regions of adjacent patches. Main array regionsinclude memory cells formed at intersections between left and rightgroups of digit lines 320 and word lines 350 a/350 b that are verticallyconnected at their respective connection locations 352 a/352 b, e.g.,respective central locations, within the socket interconnect region 312,and at intersections between left and right groups of digit lines 320and word lines 360 that are terminated within the terminating word lineregion 316. The word lines 350 a and 350 b that are vertically connectedwithin the word line interconnect socket region 312 can correspond toone of the word lines 330 a or 330 b of FIGS. 3A and 3B, and word lines360 that terminate within the terminating word line region 316 cancorrespond to the other of the word lines 330 a or 330 b of FIGS. 3A and3B. For illustrative purposes only, only a few digit lines 320 and a fewof each group of word lines 350 a/350 b and 360 are illustrated.

Still referring to FIG. 3C, in the socket interconnect region 312, theconnection locations 352 a and 352 b of vertically connected word lines350 a and 350 b are staggered, or offset in the x-direction relative toeach other. It will be appreciated that the staggered arrangement canprovide margin of error for the vertical connections. For example, whenthe vertical connections are made using via structures, a lateraldimension in the y-direction of the via structures can be greater than apitch of the word lines in the y-direction without creating anelectrical short between adjacent word lines. In the terminating wordline region 316, all word lines 360 terminate. The bundle of terminatedword lines 360 on the left side are vertically connected at theirrespective connection locations that are located at a distance of Xi tothe left of the terminating word line region 316 as described above withrespect to FIGS. 3A and 3B, and the bundle of terminated word lines 360on the right side are vertically connected at their respectiveconnection locations that are located at a distance of half of length ofthe word lines, e.g., Xi, to the right side of the terminating word lineregion 316 as described above with respect to FIGS. 3A and 3B.

While not illustrated, the tile 304 includes boundary regions betweenadjacent patches in the y-direction, each of which includes a digit linesocket interconnect region and a terminating digit line region, in ananalogous manner as described above with respect to the boundary region340 between two adjacent patches in the x-direction. As with the wordlines, vertical connections for the digit lines are made at connectionlocations (not shown) in a digit line socket interconnect region, andthose connection locations can also be staggered. Also as with the wordlines, at or within each terminating digit line region, all linesterminate (not shown).

FIG. 4A illustrates a tile 404 of memory array divided into sixteen(4×4) patches 408, and FIG. 4B illustrates one of the patches 408 of thetile 404. From a frame of reference of the illustrated tile 404, FIGS.4A and 4B illustrate four types of word lines. Word lines 430 a arevertically connected at their respective central locations at or withinone of inner word line socket interconnect regions 412 located in theupper and lower middle regions of the tile 404. Word lines 430 b arevertically connected at their respective central locations at or withinone of the word line socket interconnect regions 412 that are shifted inthe x-direction, relative to the word line socket interconnect regionconnected to the word lines 430 a, by about ¼ of a length of the wordlines, e.g., by X112, and further shifted in the y-direction by about ¼of a length of the digit lines, e.g., by Y112. Word lines 430 c and 430d have vertical connection regions that are similarly shifted in thex-direction, relative to the word line socket interconnect regionconnected to the word lines 430 a, by about ½ and ¾ of a length of theword lines (e.g., X1 and 1.5X1), respectively, and further shifted inthe y-direction by about ½ and ¾ of a length of the digit lines (e.g.,Yi and 1.5Y1), respectively. Similar to the word line socketinterconnect regions of FIGS. 3A and 3B, at a given word line socketinterconnect region 412 (FIG. 4B), some word lines are verticallyconnected (e.g., word lines 430 c and 430 d in FIG. 4B). Unlike the wordline socket interconnect regions of FIGS. 3A and 3B, however, some wordlines terminate at or within one of the word line socket interconnectregions 412 between adjacent patches (e.g., word lines 430 a and 430 bin FIG. 4B). In addition, unlike the tile 304 of FIG. 3A, the tile 404does not include terminating word line regions between adjacent patchesin the x-direction that are outside the word line socket interconnectregions 412. Instead, between adjacent patches but outside of the wordline socket interconnect regions 412, the tile 404 includes pass-throughword line regions 416, as described in more detail below with respect toFIG. 4C, through which word lines 430 a and 430 b pass without beingcontacted or terminated therein.

From a frame of reference of the illustrated tile 404, FIGS. 4A and 4Bsimilarly illustrate four types of digit line lines. Digit lines 420 aare vertically connected at their respective central locations at orwithin one of the inner digit line socket interconnect regions 414located in the right and left regions of the tile 404. In a similarmanner to the word lines, digit lines 420 b, 420 c and 420 d arevertically connected at their respective central locations at or withinone of the digit line socket interconnect regions 414 that are shiftedin the x-direction, relative to the digit line socket interconnectregion connected to the digit lines 420 a, by increments of multiples ofabout 20% to about 30% of a length of the word lines, for instance about¼, about ½ and about ¾ of a length of the word lines (e.g., X½, Xi and1.5X1), respectively, and further shifted in the y-direction byincrements of multiples of about 20% to about 30% of a length of thedigit lines, for instance about ¼, about ½ and about ¾ of a length ofthe digit lines (e.g., Y½, Y1 and 1.5Y1), respectively. In the tile 404,each digit line 430 a-430 d spans between three and about five patchesin the y-direction, for instance about four patches 408, while each wordline 420 a-420 d spans between three and five patches in thex-direction, for instance about four patches 408.

In some embodiments, within a given patch 408, word lines 430 a, 430 b,430 c and 430 d each comprise about one quarter of the number of wordlines, and digit lines 420 a, 420 b, 420 c and 420 d each comprise aboutone quarter of the number of digit lines.

FIG. 4C illustrates a detailed view of a boundary region 440 betweenmain array regions of adjacent patches 408 in the x-direction, for thearchitecture described with respect to FIGS. 4A-4B. The boundary region440 includes a word line socket interconnect region 412 and apass-through word line region 416. Similar to FIG. 3C, the boundaryregion 440 is formed between main array regions of adjacent patches.Main array regions include memory cells formed at intersections betweendigit lines 420 and word lines 450 a/450 b, 454 a/454 b and 460. Theword lines 450 a and 450 b that are connected within the word lineinterconnect socket region 412 can correspond to, e.g., the word line430 d of FIG. 4B that is connected at the word line socket interconnectregion 412 at the upper right corner region of the patch 408, and wordlines 454 a and 454 b can correspond to word line 430 b of FIG. 4B thatterminates at the upper right word line socket interconnect region 412of the patch 408. The word lines 460 can correspond to word lines 430 aand 430 c of FIGS. 4A and 4B that pass through a pass-through word lineregion 416 that is below the upper right word line socket interconnectregion 412. As can be seen, these word lines 430 a and 430 c that passthrough are connected at another (lower left) word line socketinterconnect region 412 of FIG. 4B. It will be appreciated that, forillustrative purposes only, only a few digit lines 420 and a few of eachgroup of word lines 450 a/450 b, 454 a/454 b and 460 are illustrated,but in practice each of the word line socket interconnect region 412 andthe pass-through word line region 416 can include additional word lineswithin each group.

Still referring to FIG. 4C, in the word line socket interconnect region412, the vertical connection locations 452 a and 452 b of verticallyconnected word lines 450 a and 450 b are staggered, or offset in thex-direction relative to each other, in a similar manner to FIG. 3C.Unlike the word line socket interconnect region 312 illustrated abovewith respect to FIG. 3C, the word line socket interconnect region 412includes terminating lines 454 a and 454 b that terminate within theword line socket interconnect region 412, instead of terminating linesbeing located within a terminating word line region that is outside thesocket interconnect region 412.

Still referring to FIG. 4C, the terminating lines 454 a include a firstgroup of co-terminating lines and the terminating lines 454 b include asecond group of co-terminating lines that are aligned in the x-directionand interposed in the x-direction by a gap therebetween. The verticalconnection locations 452 a and 452 b are formed within the gap. Inaddition, one or more of the vertical pass-through connections 456 a and456 b vertically pass through the gap without contacting any of the wordlines illustrated in FIG. 4C. Instead, the vertical pass-throughconnections 456 a and 456 b connect to word lines of a second deck (notshown), similar to word lines 24 described above with respect to FIG. 1Bin a multi-deck memory array. Having terminating word lines, e.g., thepairs of terminating word lines 454 a and 454 b within the socketinterconnect region allows for a relatively large room (2.5× of a pitchof the word lines in the y-direction) for the vertical pass-throughconnections 456 a/456 b. Furthermore, by choosing the number ofterminating word lines 454 a/454 b between neighboring verticalconnections 452 a/452 b in the y-direction and between neighboringvertical pass-through connections 456 a/456 b in the y-direction,corresponding connection locations to the underlying interconnectstructures can be periodically repeated in the y-direction. For example,if the word lines have a first pitch (e.g., 2 F) in the y-direction, thepositions of the vertical connections 452 a/452 b and the verticalpass-through connections 456 a/456 b can be periodically repeated in they-direction by an appropriate number of terminating word lines 454 a/454b. In the illustrated embodiment, for example, the distance in they-direction between the neighboring vertical connections is about fourtimes the first pitch, or about 8 F. Other periodicities are possible,for example greater than 6 F in increments of 2 F.

While not illustrated, the tile 404 includes boundary regions betweentwo adjacent patches in the y-direction, each of which includes a digitline socket interconnect region and an adjacent pass-through digit lineregion, in an analogous manner as described above with respect to theboundary region 440 between two adjacent patches in the x-direction. Aswith the word lines, the digit line socket interconnect region (notshown) can have vertically connected digit lines whose positions can bestaggered, terminating digit lines and vertical pass-throughconnections. As with the word lines, all lines pass through apass-through digit line region without being vertically connected orterminated.

FIG. 5A illustrates a tile 504 of memory array divided into 64 (8×8)patches, and FIG. 5B illustrates one of the patches 508 of the tile 504,according to embodiments. The tile 504 is similar to the tile 404 ofFIGS. 4A and 4B, except, from a frame of reference of the illustratedtile 504, FIGS. 5A and 5B illustrate eight types of word lines. Inaddition to the word lines 530 a vertically connected at theirrespective central locations at or within one of the word line socketinterconnect regions 512 located along the middle regions of the tile502, the tile 504 includes word lines 530 b, 530 c, 530 c, 530 d, 530 e,530 f and 530 g that are vertically connected at their respectivecentral locations at or within one of the word line socket interconnectregions 512 that are shifted in the x-direction, relative to the wordline socket interconnect region connected to the word lines 530 a, bymultiples of about ⅛ of a length of the word lines, e.g., by X¼, X½,3X¼, X1, −X¼, −X½ and −3X114, respectively, and further shifted in they-direction by about ⅛ of a length of the digit lines, e.g., by Y¼, Y½,3Y¼, Y1, −Y¼, −Y½ and −3Y¼, respectively. Similar to the word linesocket interconnect regions of FIGS. 4A and 4B, at a given word linesocket interconnect region 512, some word lines are verticallyconnected, while some word lines terminate at or within one of the wordline socket interconnect regions 512 between adjacent patches. However,as described more in detail with respect to FIG. 5C, unlike the tile 404of FIG. 4A, the tile 504 not only includes connected and terminatingword lines that connect and terminate in a word line socket interconnectregion 512, but additionally includes pass-through word lines within thesame socket interconnect region 512.

From a frame of reference of the illustrated tile 504, FIGS. 5A and 5Bsimilarly illustrate eight types of digit lines. In addition to thedigit lines 520 a vertically connected at their respective centrallocations at or within one of the digit line socket interconnect regions514 located along the middle regions of the tile 504, the tile 504includes digit lines 520 b, 520 c, 520 c, 520 d, 520 e, 520 f and 520 gthat are vertically connected at their respective central locations ator within one of the digit line socket interconnect regions 514 that areshifted in the x-direction, relative to the word line socketinterconnect region 514 connected to the word lines 530 a, by incrementsof multiples of about 5% to about 20% of a length of the word lines orincrements of multiples of about 10% to about 15% of a length of theword lines, for instance of about ⅛ of a length of the word lines (e.g.,by X114, X112, 3X114, X1, −X114, −X112 and −3X114, respectively), andfurther shifted in the y-direction by increments of multiples of about5% to about 20% of a length of the digit lines or increments ofmultiples of about 10% to about 15% of a length of the digit lines, forinstance about ⅛ of a length of the digit lines (e.g., by Y114, Y112,3Y¼, Y1, −Y¼, −Y112 and −3Y114, respectively). In the tile 504, eachdigit line 520 a-h spans between six and ten patches in the y-direction,or between seven and eight patches, for instance about eight patches508, while each word line 530 a-h spans between six and ten patches inthe x-direction, or between seven and eight patches, for instance abouteight patches 508. Correspondingly, each digit line 520 a-h spans acrossa length corresponding to between five and nine adjacent digit linesocket interconnect regions 514 in the y-direction, or between six andeight digit line socket interconnect regions 514, for instance aboutseven digit line socket interconnect regions 514, while each word line530 a-h spans across a length corresponding to between five and nineadjacent word line socket interconnect regions 512 in the x-direction,or between six and eight word line socket interconnect regions 512, forinstance about seven word line socket interconnect regions 512.

In some embodiments, within a given patch 508, digit lines 520 a-h eachcomprise about one eighth (⅛) of the number of word lines, and wordlines 530 a-h each comprise about one eighth (⅛) of the number of digitlines.

FIG. 5C illustrates a detailed view of a boundary region 540 betweenmain array regions of adjacent patches 508 in the x-direction, for thearchitecture of FIGS. 5A-5B. The boundary region 540 includes a wordline socket interconnect region 512 and a pass-through word line region516. Similar to FIG. 4C, the boundary region 540 is formed between mainarray regions of adjacent patches, in which memory cells are formed atintersections between digit lines 520 and word lines 550 a/550 b, 554a/554 b, 558 and 560.

Still referring to FIG. 5C, in the word line socket interconnect region512, the vertical connections are made at connection locations 552 a and552 b of vertically connected word lines 550 a and 550 b, where theconnection locations are staggered, or offset in the x-directionrelative to each other, in a similar manner to FIG. 4C. In addition, aplurality of terminating lines 554 a/554 b terminate at or within theword line socket interconnect region 512. In the illustrated embodiment,the terminating lines 554 a/554 b include at least two lines thatco-terminate. Unlike the word line socket interconnect regionillustrated above with respect to FIG. 4C, the word line socketinterconnect region 512 includes pass-through word lines 558 thatpass-through the word line socket interconnect region 512 without beingvertically connected and without being terminated at the socketinterconnect region 512. The pass-through word lines 558 are in additionto pass-through word lines 560 that pass through the pass-through wordline region 516 that is vertically adjacent and located outside of theword line socket interconnect region 512. The pass-through word lines558 are distinguishable from the pass-through word lines 560 by thelocation of their vertical connection. The pass-through word lines 558of the illustrated embodiment are located between connected word lines550 a and 550 b in the same socket interconnect region 512, and alsobetween terminated word lines 554 b or 554 a in the same socketinterconnect region 512.

Still referring to FIG. 5C, similar to the arrangement described abovewith respect to FIG. 4C, the terminating lines 554 a include a firstgroup of co-terminating lines and the terminating lines 554 b include asecond group of co-terminating lines that are aligned in the x-directionand interposed in the x-direction by a gap therebetween. The verticalconnection locations 552 a and 552 b are formed within the gap. Inaddition, one or more of vertical pass-through connections 556 a and 556b vertically pass through the gap without contacting any of the wordlines illustrated in FIG. 5C. Instead, the vertical pass-throughconnections 556 a and 556 b connect to word lines of a second deck (notshown), in a similar manner to as described above with respect to FIG.4C. Similar to as described above with respect to FIG. 4C, havingterminating word lines, e.g., the pairs of terminating word lines 554 aand 554 b within the socket interconnect region allows for a relativelylarge room (2.5× of a pitch of the word lines in the y-direction) forthe vertical pass-through connections 556 a/556 b. Furthermore, bychoosing the number of pass-through word lines 558 and terminating wordlines 554 a/554 b between neighboring vertical connections 552 a/552 bin the y-direction and between neighboring vertical pass-throughconnections 556 a/556 b in the y-direction, corresponding connectionlocations to the underlying interconnect structures can be periodicallyrepeated in the y-direction. For example, if the word lines have a firstpitch (e.g., 2 F) in the y-direction, the positions of the verticalconnections 552 a/552 b can be periodically repeated in the y-directionby an appropriate number of intervening pass-through word lines 558 andterminating word lines 554 a/554 b. In the illustrated embodiment, forexample, the distance in the y-direction between the neighboringvertical connections 552 a/552 b and between neighboring verticalpass-through connections 556 a/556 b is about eight times the firstpitch, or about 16 F. Other periodicities are possible, for examplegreater than 6 F in increments of 2 F.

FIG. 5D is a detailed view of multiple boundary regions 540 a ofadjacent patches 508 in the x-direction, for illustration of relativelocations of termination, vertical connection and pass-through locationsof the various lines described above with respect to FIG. 5C. FIG. 5Dillustrates a plurality of word lines 530 a-530 h, wherein each wordline extends in the x-direction and is vertically connected at adifferent socket interconnect region 512 (two labeled 512 a and 512 b inFIG. 5D) that are shifted with respect to each other. In FIG. 5D, whilea single word line is shown for each of the word lines 530 a-530 h, eachof the word lines 530 a-530 h can represent a plurality (e.g., 2, 4, 8,etc.) of word lines that co-terminate and are vertically connected atthe same socket interconnect region. It is noted the word lines 530a-530 h are vertically connected at a word line socket interconnectregion of one of eight consecutive patches 508 that are shifted withrespect to one another in the x-direction but not in the y-direction.Thus, like numeral designations of word lines between FIGS. 5A and 5D donot necessarily correspond to one another. An amount of the shift in thex-direction of a first socket interconnect region 512 a (correspondingto a vertical connection location of the word line 530 a) relative to asecond socket interconnect region 512 b (corresponding to a verticalconnection location of the word line 530 b) is between about 1/32 andabout ¼ of a length of the word lines, or between is between about 1/16and about 3/16 of the length of the word lines, for instance about ⅛ ofthe length of the word lines. Referring to FIGS. 5C and 5D, verticallyconnected word lines 550 a and 550 b of FIG. 5C can correspond to one ofthe word lines 530 a of FIG. 5D that are connected at word line socketinterconnect regions 516 a, and terminating word lines 554 a and 554 bof FIG. 5C can correspond to one of the word lines 530 ethat terminateat the word line socket interconnect regions 512 a (FIG. 5D).

Referring to FIG. 5D, it will be appreciated that the pass-through wordlines that pass through a word line socket interconnect region (e.g.,512 a) are distinguishable from pass-through word lines that passthrough a pass-through word line region (e.g., 516 a) by theirrespective vertical connection locations. Referring to the socketinterconnect region 512 in which the word line 530 e is centrallyconnected, word lines 530 c and 530 g that pass through the socketinterconnect region 512 a are connected two patches away, e.g., betweenabout 3/16 and about 5/16 of a length of the word lines (e.g., betweenabout X¼ and about 3X¼) away, for instance about ¼ of a length of theword lines (e.g., X½) away, from the socket interconnect region 512 a ofthe word line 530 e. In contrast, word lines 540 b, 540 d, 540 f and 540h that pass through the pass-through word line region 516 a below thesocket interconnect region 512 a in which the word line 530 e iscentrally connected are connected at distances that are different fromthe pass-through word lines 558, e.g., different than two patches away,e.g., one or three patches away, corresponding to about ⅛ and about ⅜ ofa length of the word lines (e.g., X¼ and 3X¼), respectively, from thesocket interconnect region 512 a in which the word line 530 e iscentrally connected.

While not illustrated, the tile 504 includes boundary regions betweentwo adjacent patches in the y-direction, each of which includes a digitline socket interconnect region and an adjacent pass-through digit lineregion, in an analogous manner as described above with respect to theboundary region 540 between two adjacent patches in the x-direction. Aswith the word lines, the digit line socket interconnect region can havevertically connected digit lines (not shown) whose positions can bestaggered, have terminating digit lines and vertical pass-throughconnections and have pass-through digit lines. As with the word lines,all lines pass-through a given pass-through digit line socketinterconnect region without being vertically connected or terminated.

It will be appreciated that having the various arrangements describedabove with respect to FIGS. 4A-3C, 4A-4C and 5A-5D is more than meredesign choice. Location for the driver circuitry affects performance ofthe memory and requires substantial architectural changes, as explainedbelow with respect to FIG. 6A-6C, in the array and metallization layers.

It will be appreciated that for the various arrangements described abovewith respect to FIGS. 2A-2B, 3A-3C, 4A-4C and 5A-5D, sometimes referredto as “quilt architectures,” substantial cost reduction can be achievedby fitting all drivers under the array, sharing the same footprint asmemory cells in a densely packed manner, as compared to arrangements inwhich drivers are located at or outside the periphery of the array. Thevarious arrangements place all drivers under the array by breaking upthe driver groups into smaller pieces and locating the sockets in adistributed manner. In addition, by driving the electrode lines fromtheir midpoints may confer advantages to drivers due to reduction in IRdrop and RC delay as compared to conventional techniques, because thefarthest cell along the line is about half the distance as for thefarthest cell for electrode lines driven from their endpoints, which canbe of significant benefit to certain types of cross-point memory celltechnologies. Benefits may be manifested in relaxed transistorrequirements, circuit complexity, process complexity or circuit area forthe driver circuits, as examples.

Furthermore, the architectures of FIGS. 3A-3C, 4A-4C and 5A-5D permitbreaking the device driver groups, the array, and socket interconnectregions into successively smaller pieces, which can be associated withsuccessively relaxed pitch requirement of interconnect metal layersvertically adjacent the electrode lines, resulting in successivelyincreasing cost advantage, as described below with respect to FIGS.6A-6C. In addition, successively relaxed pitch requirement can beassociated with successive lower resistance and RC delays associatedwith the interconnect metal layers and other connected structures suchas vias. In the following, the advantageous relaxation of lithographicpitch of the interconnect levels is illustrated with reference to FIG.5D and FIGS. 6A-6C. In the illustrated examples, a plurality ofelectrode lines, e.g., word lines, are formed at a word line layer leveland extend in a first lateral direction (e.g., x-direction in FIG. 5D)to traverse a plurality of array patches and a plurality of boundaryregions, wherein each boundary region includes one or more socketinterconnect regions (e.g., 512 a in FIG. 5D) and one or morepass-through electrode regions (e.g., 516 a in FIG. 5D). Each patch isformed between socket interconnect regions that are adjacent in alateral direction (e.g., x-direction). Vertical connections to theelectrode lines are made in the socket interconnect regions, but not inthe patch regions between socket interconnect regions. Each of theelectrode lines, e.g., word lines, is vertically connected to ametallization level formed at a second vertical level, e.g., avertically adjacent interconnect level, at one of the socketinterconnect regions. By staggering connection positions of successiveelectrode lines so that they are laterally offset from each other (e.g.,in the x-direction in FIG. 5D), and having the connection positionsperiodically repeat in a second lateral direction (e.g., y-direction inFIG. 5D), the lithographic tolerance requirements of the connectionbetween the word line layer level and the vertically adjacentinterconnect level can be relaxed. The amount of relaxation can becustomized based on the periodicity of the periodically repeatingpositions, whose periodicity is which is greater than a pitch of theelectrode lines multiplied by a number of patches traversed by eachelectrode line. For example, in FIGS. 6A, 6B and 6C, the number ofpatches traversed by the electrode lines is 2 in FIG. 6A, 4 in FIG. 6Band 8 in FIG. 6C, which relaxes the lithographical pitches of thevertically adjacent interconnect level to 4 F, 8 F and 16 F,respectively, wherein the pitch of the word lines is 2 F. The conceptsdescribed herein can be extended to vertical connections between wordlines and the vertically adjacent interconnect level connections, and tovertical connections between bit lines/word lines and interconnectlevels that are not immediately adjacent.

FIGS. 6A, 6B and 6C are cross-sectional illustrations of memory devices600 a, 600 b and 600 c, corresponding to memory devices having tiles304, 404 and 504 of memory array described above with respect to FIGS.3A-3C, 4A-4C and 5A-5D, respectively. Each of the memory devices 600 a,600 b and 600 c has a memory array which includes a respective digitline (DL) layer, which is referred to herein as a bit line (BL) layer620 a, 620 b and 620 c, and a respective word line (WL) layer 622 a, 622b, and 622 c, and memory cells (not shown for clarity) formed at theintersections of word lines and digit lines that cross each other. Eachof the memory devices 600 a-600 c has a respective transistor level 642a, 642 b and 642 c, which includes driver transistors. The transistorlevels 642 a, 642 b and 642 c are connected to respective level 1metallization (M1) levels 638 a, 638 b and 638 c through a respectivecontact via structure 640 a, 640 b and 640 c, and respective level 2metallization (M2) levels 634 a, 634 b and 634 c are connected torespective M1 levels 638 a, 638 b and 638 c through respective M1-M2 viastructures 636 a, 636 b and 636 c. The arrays of each of the memorydevices 600 a, 600 b and 600 c and the respective M2 levels 634 a, 634 band 634 c are connected through an interconnect level 630 a, 630 b and630 c. The function of the interconnect levels 630 a, 630 b and 630 c isto electrically connect the array with the transistors through one ormore metallization levels (e.g., M1 and M2). In some embodiments, aninterconnect level may itself be a metallization layer. On the arrayside, the interconnect levels 630 a, 630 b and 630 c are connected tothe respective BL levels 620 a, 620 b and 630 c through respective digitline (BL) layer array vias 624 a, 624 b and 624 c, and are connected tothe respective WL levels 622 a, 622 b and 622 c through respective wordline (WL) layer array vias 626 a, 626 b and 626 c. On the metallizationside, the interconnect levels 630 a, 630 b and 630 c are connected tothe respective M2 levels 634 a, 634 b and 634 c through respectiveinterconnect vias 632 a, 632 b and 632 c. In FIGS. 6A, 6B and 6C, forclarity of description only, only one conductive structure correspondingto each of the various via layers is illustrated.

Forming vertical connections to electrode lines as using one of socketinterconnect designs illustrated in FIGS. 3C, 4C and 5C may affectdesign rules for one or more of the BL layer array vias 624 a-624 c, theWL layer array vias 626 a-626 c, the interconnect levels 630 a-630 c andthe interconnect vias 632 a-632 c.

For example, in designing a socket interconnect region similar to theword line socket interconnect region 312 described above with respect toFIG. 3C, if a pitch of electrode lines, e.g., the word lines and thedigit lines, is represented as 2 F, where F is a minimum lithographicfeature size, the vertical connection locations 352 a or 352 b has aperiodicity in the y-direction of 4 F. As a result, in order to makeconnections to each of the vertical connection locations 352 a and 352 bin the word line socket region 312 of FIG. 3C, metal lines having apitch of 4 F would typically be employed at the interconnect level 630 aof the device 600 a of FIG. 6A. In addition, via connections to suchmetal lines would generally follow similar or same feature size designrules. Thus, with reference to FIG. 6A, a feature size design rule forpatterning the BL layer array via 624 a, the WL layer array via 626 a,the interconnect level 630 a and the interconnect via 632 a would beabout 4 F, which is twice the pitch of the array electrode lines. As anillustrative example, for an array electrode pitch of 32 nm, pitch ofmetal lines of the interconnect level 630 a would be about 64 nm. Thisfeature size design rule can be substantially relaxed, however, bydesigning a socket interconnect region similar to the word line socketinterconnect regions 412 (FIG. 4C) and 512 (FIG. 5C), as describedbelow.

Referring to FIG. 6B, in designing a socket interconnect region similarto the word line socket interconnect region 412 described above withrespect to FIG. 4C, for an array electrode line pitch of 2 F, each ofthe vertical connection locations 452 a and 452 b (FIG. 4C) has aperiodicity in the y-direction of 8 F. In addition, each of the verticalpass-through connections 456 a and 456 b (FIG. 4C) has a periodicity inthe y-direction of 8 F. As a result, for similar reasons as describedabove with respect to FIG. 6A, to connect the vertical connectionlocations 452 a and 452 b and/or the vertical pass-through connections456 a and 456 b at the interconnect level 630 b, metal lines having apitch of greater than 6 F, e.g., 8 F (4× the pitch of the arrayelectrode lines), can be employed, which would correspondingly constrainfeature sizes of the BL layer array via 624 b, the WL layer array via624 b, the interconnect level 630 b and the interconnect via 632 b. Asan illustrative example, for an array electrode pitch of 32 nm, pitch ofmetal lines of the interconnect level 630 a could be greater than 3×this pitch, or greater than about 96 nm, e.g., 4× the array pitch (about128 nm). This feature size design rule can be further relaxed bydesigning a socket interconnect region similar to the word line socketinterconnect region 512 of FIG. 5C, as described below.

Referring to FIG. 6C, in designing a socket interconnect region similarto the word line socket interconnect region 512 described above withrespect to FIG. 5C, for an array electrode line pitch of 2 F, thevertical connection locations 552 a or 552 b has a periodicity in they-direction of 16 F. In addition, the vertical pass-through connections556 a and 556 b also has a periodicity in the y-direction of 16 F. As aresult, for similar reasons as described above with respect to FIG. 6B,to connect each of the vertical connection locations 552 a and 552 band/or the each of vertical pass-through connections 556 a and 556 b atthe interconnect level 630 c, metal lines having a pitch of greater than8 F, and particularly greater than 12 F, e.g., about 16 F (which is 8×the pitch of the array electrode lines), could be employed, which wouldcorrespondingly constrain feature sizes of the BL layer array via 624 c,the WL layer array via 624 c, the interconnect level 630 c and theinterconnect via 632 c. As an illustrative example, for an arrayelectrode pitch of 32 nm, pitch of metal lines of the interconnect level630 a could be greater than 6× this pitch, or greater than about 192 nm,e.g., 8× the array pitch (about 256 nm). It will be appreciated that theincrease in the pitch of the metal lines of the interconnect level bygreater than three times the pitch of the electrode lines as describedabove can enable substantial cost savings by, for example, relaxing thedemands on lithography relative to critical lithography processes forseveral structures, such as metal lines of the interconnect level, digitline (BL) layer array vias, word line (WL) layer array vias andinterconnect vias. For example, when the pitch of metal lines is 192 nm,193 nm UV excimer laser may be employed for patterning without pitchdoubling, and when the pitch of metal lines is 256 nm, 248 nm UV excimerlaser may be employed for patterning without pitch doubling.

While there has been illustrated and described what are presentlyconsidered to be example features, it will be understood by thoseskilled in the art that various other modifications may be made, andequivalents may be substituted, without departing from claimed subjectmatter. Additionally, many modifications may be made to adapt aparticular situation to the teachings of claimed subject matter withoutdeparting from the central concept described herein. Therefore, it isintended that claimed subject matter not be limited to the particularexamples disclosed, but that such claimed subject matter may alsoinclude all aspects falling within the scope of appended claims, andequivalents thereof.

What is claimed is:
 1. A memory device, comprising: a plurality ofelectrode lines at a first level, the plurality of electrode linesextending in a first direction and having a first pitch in a seconddirection, wherein each electrode line is connected at a connectionposition in the first direction, wherein each electrode line isconnected to one of a plurality of metal lines of an interconnect levelabove or below the first level in a third direction, and wherein theconnection positions of at least some of the plurality of electrodelines periodically repeat in the second direction at a periodicity thatis greater than the first pitch.
 2. The memory device of claim 1,wherein the plurality of metal lines is electrically connected with atransistor level below the interconnect level in the third direction. 3.The memory device of claim 1, wherein the periodicity of repeatingconnection positions is about or greater than 8 F, F being a minimumlithographic feature size.
 4. The memory device of claim 3, wherein theplurality of metal lines of the interconnect level extend in the seconddirection and have a second pitch that is the same as the periodicity ofthe repeating connection positions.
 5. The memory device of claim 4,wherein the second pitch is about 16 F.
 6. The memory device of claim 1,wherein: the third direction is perpendicular to the first direction andto the second direction, or the third direction crosses the firstdirection and the second direction and is non-perpendicular to the firstdirection and to the second direction.
 7. An integrated circuit,comprising: a plurality of conductive lines formed at a first level thatextend in a first direction and have a pitch in a second direction,wherein the plurality of conductive lines are connected to interconnectstructures formed at a second level above or below the first level in athird direction, the plurality of conductive lines comprising: a firstplurality of lines connected to at least one interconnect structure at asocket interconnect region; a second plurality of lines connected to thesocket interconnect region; and a third plurality of lines that passthrough the socket interconnect region.
 8. The integrated circuit ofclaim 7, wherein the third plurality of lines pass through the socketinterconnect region without being connected to the socket interconnectregion and without being terminated at or within the socket interconnectregion.
 9. The integrated circuit of claim 7, wherein the secondplurality of lines comprise: a first group of co-terminating lines; anda second group of co-terminating lines that are aligned in the firstdirection and interposed in the first direction by a gap within thesocket interconnect region, wherein at least one connector passesthrough the gap without contacting any of the plurality of conductivelines at the first level.
 10. The integrated circuit of claim 9, furthercomprising: a plurality of upper conductive lines extending in the firstdirection formed at a third level above the first level, wherein the atleast one connector electrically connects one of the plurality of upperconductive lines to the at least one interconnect structure.
 11. Theintegrated circuit of claim 7, wherein the plurality of conductive linesare word lines or digit lines of a first memory array deck and upperconductive lines serve as word lines or digit lines of a second memoryarray deck.
 12. The integrated circuit of claim 7, further comprising:phase change memory cells positioned at intersections between theplurality of conductive lines and digit lines.
 13. The integratedcircuit of claim 7, wherein at least one connector is positioned betweena first pair of contacted lines and extends the third direction.
 14. Theintegrated circuit of claim 7, wherein a line of the second plurality oflines is connected to an interconnect structure of a second socketinterconnect region that is offset from the socket interconnect regionin the first direction.
 15. The integrated circuit of claim 7, whereineach of the first plurality of lines, the second plurality of lines andthe third plurality of lines have substantially the same length in thefirst direction.
 16. The integrated circuit of claim 7, wherein: thethird direction is perpendicular to the first direction and to thesecond direction, or the third direction crosses the first direction andthe second direction and is non-perpendicular to the first direction andto the second direction.
 17. A memory array, comprising: a plurality ofelectrode lines formed at a first level and traversing a plurality ofmemory cell regions, each memory cell region formed between socketinterconnect regions in a first direction, wherein the plurality ofelectrode lines have a pitch in a second direction and include digitlines and word lines that intersect in the plurality of memory cellregions, wherein each electrode line is coupled with a second levelabove or below the first level in a third direction using at least onesocket interconnect region.
 18. The memory array of claim 17, whereinconnection positions of groups of the plurality of electrode lines areoffset from each other in the first direction and are periodicallyrepeating in the second direction.
 19. The memory array of claim 18,wherein a periodicity of the periodically repeating positions is greaterthan a pitch of the plurality of electrode lines multiplied by a numberof memory cell regions traversed by the plurality of electrode lines.20. The memory array of claim 17, wherein: the third direction isperpendicular to the first direction and to the second direction, or thethird direction crosses the first direction and the second direction andis non-perpendicular to the first direction and to the second direction.